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rev. 0.5 10/08 copyright ? 2008 by silicon laboratories si473x-b20 si473x-b20 b roadcast m ulti -b and r adio r eceiver features applications si473x product selector guide ? fm band support: 76?108 mhz ? am band support: 520?1710 khz ? sw band support: 2.3?21.85 mhz (si4734/35) ? lw band support: 153?279 khz (si4734/35) ? weather band support: 162.4? 162.55 mhz (si4736/37/38/39) ? 1050 hz alert tone detection (si4736/37/38/39) ? excellent real-world performance ? freq synthesizer with integrated vco ? advanced seek tuning ? automatic frequency control (afc) ? automatic gain control (agc) ? integrated ldo regulator ? digital fm stereo decoder ? programmable de-emphasis ? adaptive noise suppression ? am/fm digital tuning ? en55020 compliant ? no manual alignment necessary ? programmable reference clock ? volume control ? programmable soft mute control ? rds/rbds processor (si4731/35/37/39) ? optional digital audio output (si4731/35/37/39) ? 2-wire control interface ? 2.7 to 5.5 v supply voltage ? firmware upgradeable ? wide range of ferrite loop sticks and air loop antennas supported ? 3 x 3 x 0.55 mm 20-pin qfn package ? pb-free/rohs compliant ? table and portable radios ? audio video receivers ? stereos ? mini/micro systems ? cd/dvd players ? portable media players ? cellular handsets ? emergency radios ? clock radios ? modules ? mini hifi ? boom boxes part fm am rds sw/lw wb si4730 76 ? 108 mhz ? si4731 76 ? 108 mhz ?? si4734 64 ? 108 mhz ?? si4735 64 ? 108 mhz ??? si4736 76 ? 108 mhz ?? si4737 76 ? 108 mhz ?? ? si4738 76 ? 108 mhz ? si4739 76 ? 108 mhz ?? patents pending notes: 1. place si473x as close as possible to antenna jack and keep the fmi and ami traces as short as possible. 2. contact your local sales representatives for more information or to obtain application notes. ordering information: see page 18. pin assignments gnd pad 1 2 3 17 18 19 20 11 12 13 14 6 7 8 9 4 5 16 10 15 gpo2/int vio dout lout rout gnd rst nc ami rclk sdio vdd fmi rfgnd gpo3/dclk nc gpo1 dfs sclk sen si473x-gm (top view)
si473x-b20 2 rev. 0.5
si473x-b20 rev. 0.5 3 t able of c ontents section page 1. product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3. typical am/fm application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4. bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5. pin descriptions: si473x-gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7. package outline: si473x qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8. pcb land pattern: si473x qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9. additional reference resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
si473x-b20 4 rev. 0.5 1. product overview the si473x receivers are the industry's first fully-integra ted multiband radio receiver ics from antenna input to audio output. they require minimal external components with no factory alignment. the si473x receivers reduce the receiver footprint by >90% versus traditional am/fm solutions. the si473x also offer best-in-class performance with the most features. the high integration and complete system production test simplifies design-in, increases system quality, and impr oves manufacturability. the si473x receivers include advanced seek algorithms, adjustable soft mute, auto-calibrated digital tuning, and fm stereo processing. in addition, t he si473x ics provide a programmable reference clock and an i2c-compatible 2-wire control interface. the si4731/35/37/39 incorporates a digital processor for the european radi o data system (rds) and the north american radio broadcast data system (rbds), includin g all required symbol decoding, block synchronization, error detection, and error correction functions. using these features, the si4731/35/37/39 enables broadcast data such as station identification and song name to be displayed to the end user. 2. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max unit supply voltage v dd 2.7 ? 5.5 v interface supply voltage v io 1.5 ? 3.6 v power supply powe rup rise time v ddrise 10 ? ? s interface power supply powerup rise time v iorise 10 ? ? s ambient temperature t a ?20 25 85 ? c note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at v dd = 3.3 v and 25 ? c unless otherwise stated. parameters are tested in production unless otherwise stated.
si473x-b20 rev. 0.5 5 table 2. absolute maximum ratings 1,2 parameter symbol value unit supply voltage v dd ?0.5 to 5.8 v interface supply voltage v io ?0.5 to 3.9 v input current 3 i in 10 ma input voltage 3 v in ?0.3 to (v io + 0.3) v operating temperature t op ?40 to 95 ? c storage temperature t stg ?55 to 150 ? c rf input level 4 0.4 v pk notes: 1. permanent device damage may occur if the above absolu te maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. the si473x devices are high-performance rf integrated circuits with certain pins having an esd rating of < 2 kv hbm. handling and assembly of these devices sh ould only be done at esd-protected workstations. 3. for input pins sclk, sen, sdio, rst, rcl k, dclk, dfs, gpo1, gpo2, and gpo3. 4. at rf input pins, fmi and ami.
si473x-b20 6 rev. 0.5 table 3. dc characteristics (v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit fm mode supply current i fm ?19.222ma supply current 1 i fm low snr level ? 19.8 23 ma rds supply current 2 i fm ?19.923ma wb mode (si4736/37/38/39 only) supply current i fm ?19.222ma supply current 1 i fm low snr level ? 19.8 23 ma am mode (si4730/31/34/35/36/37 only) supply current i am ? 17.3 20.5 ma supplies and interface interface supply current i io ?320600a v dd powerdown current i ddpd ?1020 a v io powerdown current i iopd sclk, rclk inactive ? 1 10 a high level input voltage 3 v ih 0.7 x v io ?v io +0.3 v low level input voltage 3 v il ?0.3 ? 0.3 x v io v high level input current 3 i ih v in = v io = 3.6 v ?10 ? 10 a low level input current 3 i il v in =0v, v io =3.6v ?10 ? 10 a high level output voltage 4 v oh i out = 500 a 0.8 x v io ??v low level output voltage 4 v ol i out = ?500 a ? ? 0.2 x v io v notes: 1. lna is automatically switched to higher current mode for optimum sensitivity in weak signal conditions. 2. specifications are guaran teed by characterization. 3. for input pins sclk, sen, sdio, rst, rclk, dclk, and dfs. 4. for output pins sdio, dout, gpo1, gpo2, and gpo3.
si473x-b20 rev. 0.5 7 figure 1. reset timing parameters for busmode select table 4. reset timing characteristics 1,2 (v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol min typ max unit rst pulse width and gpo1, gpo2/int setup to r st ? ? t srst 100 ? ? s gpo1, gpo2/int hold from r st ? t hrst 30 ? ? ns important notes: 1. when selecting 2-wire mode, the user must ensure that a 2- wire start condition (falling edge of sdio while sclk is high) does not occur within 300 ns before the rising edge of rst . 2. when selecting 2-wire mode, the user must ensure t hat sclk is high during the rising edge of rst , and stays high until after the first start condition. 3. if gpo1 and gpo2 are actively driven by the user, then minimum t srst is only 30 ns. if gpo1 or gpo2 is hi-z, then minimum t srst is 100 s to provide time for on-chip 1 m ? devices (active while rst is low) to pull gpo1 high and gpo2 low. 70% 30% gpo1 70% 30% gpo2/ int 70% 30% t srst rst t hrst
si473x-b20 8 rev. 0.5 table 5. 2-wire control interface characteristics 1,2,3 (v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit sclk frequency f scl 0?400khz sclk low time t low 1.3 ? ? s sclk high time t high 0.6 ? ? s sclk input to sdio ? setup (start) t su:sta 0.6 ? ? s sclk input to sdio ? hold (start) t hd:sta 0.6 ? ? s sdio input to sclk ? setup t su:dat 100 ? ? ns sdio input to sclk ? hold 4,5 t hd:dat 0?900ns sclk input to sdio ? setup (stop) t su:sto 0.6 ? ? s stop to start time t buf 1.3 ? ? s sdio output fall time t f:out ?250ns sdio input, sclk rise/fall time t f:in t r:in ?300ns sclk, sdio capacitive loading c b ??50pf input filter pu lse suppression t sp ? ? 50 ns notes: 1. when v io = 0 v, sclk and sdio are low impedance. 2. when selecting 2-wire mode, the user must ensure that a 2- wire start condition (falling edge of sdio while sclk is high) does not occur within 300 ns before the rising edge of rst . 3. when selecting 2-wire mode, the user must ensure th at sclk is high during the rising edge of rst , and stays high until after the first start condition. 4. the si473x delays sdio by a minimum of 300 ns from the v ih threshold of sclk to comply with the minimum t hd:dat specification. 5. the maximum t hd:dat has only to be met when f scl = 400 khz. at frequencies below 400 khz, t hd:dat may be violated as long as all other timing parameters are met. 20 0.1 c b 1pf ---------- - + 20 0.1 c b 1pf ---------- - +
si473x-b20 rev. 0.5 9 figure 2. 2-wire control interface read and write timing parameters figure 3. 2-wire control interface read and write timing diagram sclk 70% 30% sdio 70% 30% start start stop t f:in t r:in t low t high t hd:sta t su:sta t su:sto t sp t buf t su:dat t r:in t hd:dat t f:in, t f:out sclk sdio start stop address + r/w ack data ack data ack a6-a0, r/w d7-d0 d7-d0
si473x-b20 10 rev. 0.5 figure 4. digital audio interface timing parameters, i 2 s mode table 6. digital audio interface characteristics (v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit dclk cycle time t dct 26 ? 1000 ns dclk pulse width high t dch 10 ? ? ns dclk pulse width low t dcl 10 ? ? ns dfs set-up time to dclk rising edge t su:dfs 5?? ns dfs hold time from dclk rising edge t hd:dfs 5?? ns dout propagation delay from dclk falling edge t pd:dout 0?12ns dclk dfs t dct t pd:out t su:dfs t hd:dfs dout t dch t dcl
si473x-b20 rev. 0.5 11 table 7. fm receiver characteristics 1,2 (v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit input frequency f rf 76 ? 108 mhz sensitivity with headphone network 3,4,5 (s+n)/n = 26 db ? 2.2 3.5 v emf sensitivity with 50 ? network 3,4,5,6 (s+n)/n = 26 db ? 1.1 ? v emf rds sensitivity 6 ? f = 2 khz, rds bler < 5% ?15?v emf lna input resistance 6,7 345 k ? lna input capacitance 6,7 456 pf input ip3 6,8 100 105 ? dbv emf am suppression 3,4,6,7 m = 0.3 40 50 ? db adjacent channel selectivity 200 khz 35 50 ? db alternate channel selectivity 400 khz 60 70 ? db spurious response rejection 6 in-band 35 ? ? db audio output voltage 3,4,7 72 80 90 mv rms audio output l/r imbalance 3,7,9 ?? 1 db audio frequency response low 6 ?3 db ? ? 30 hz audio frequency response high 6 ?3 db 15 ? ? khz audio stereo separation 7,9 25 ? ? db audio mono s/n 3,4,5,7,10 55 63 ? db audio stereo s/n 4,5,7,10,11 ?58? db audio thd 3,7,9 ?0.10.5 % de-emphasis time constant 6 fm_deemphasis = 2 70 75 80 s fm_deemphasis = 1 45 50 54 s audio output load resistance 6,10 r l single-ended 10 ? ? k ? audio output load capacitance 6,10 c l single-ended ? ? 50 pf notes: 1. additional testing information is available in ?an388: si470x/1x/2x/3x/4x evaluatio n test board procedure.? volume = maximum for all tests. tested at rf = 98.1 mhz. 2. to ensure proper operation and receiver performance, follo w the guidelines in ?an383: si47xx antenna, schematic, layout and design guidelines.? silicon laboratories will evaluate schematics and layo uts for qualified customers. 3. f mod =1khz, 75 s de-emphasis, mono = enabled, and l = r unless noted otherwise. 4. ? f = 22.5 khz. 5. b af = 300 hz to 15 khz, a-weighted. 6. guaranteed by characterization. 7. v emf =1 mv. 8. |f 2 ? f 1 | > 2 mhz, f 0 =2xf 1 ? f 2 . agc is disabled. 9. ? f = 75 khz. 10. at l out and r out pins. 11. analog audio output mode. 12. at temperature (25c).
si473x-b20 12 rev. 0.5 seek/tune time 6 rclk tolerance =100ppm ? ? 80 ms/channel powerup time 6 from powerdown ? ? 110 ms rssi offset 12 input levels of 8 and 60 dbv at rf input ?3 ? 3 db table 7. fm receiver characteristics 1,2 (continued) (v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit notes: 1. additional testing information is available in ?an388: si470x/1x/2x/3x/4x evaluatio n test board procedure.? volume = maximum for all tests. tested at rf = 98.1 mhz. 2. to ensure proper operation and receiver performance, follo w the guidelines in ?an383: si47xx antenna, schematic, layout and design guidelines.? silicon laboratories will evaluate schematics and layo uts for qualified customers. 3. f mod =1khz, 75 s de-emphasis, mono = enabled, and l = r unless noted otherwise. 4. ? f = 22.5 khz. 5. b af = 300 hz to 15 khz, a-weighted. 6. guaranteed by characterization. 7. v emf =1 mv. 8. |f 2 ? f 1 | > 2 mhz, f 0 =2xf 1 ? f 2 . agc is disabled. 9. ? f = 75 khz. 10. at l out and r out pins. 11. analog audio output mode. 12. at temperature (25c).
si473x-b20 rev. 0.5 13 table 8. am/sw/lw receiver characteristics 1 (v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, ta = ?20 to 85 c) parameter symbol test condition min typ max unit input frequency f rf long wave (lw) 153 ? 279 khz medium wave (am) 520 ? 1710 khz short wave (sw) 2.3 ? 21.85 mhz sensitivity 2,3,4,5, 6 (s+n)/n = 26 db ? 25 35 v emf large signal voltage handling 5,7 thd < 8% ? 300 ? mv rms power supply rejection ratio v dd =100 mv rms , 100 hz ? 40 ? db audio output voltage 2,8 54 60 67 mv rms audio s/n 2,3,4,6,8 50 56 ? db audio thd 2,4,8 ? 0.1 0.5 % antenna inductance long wave (lw) ? 2800 ? h medium wave (am) 180 ? 450 powerup time from powerdown ? ? 110 ms notes: 1. to ensure proper operation and receiver performance, follo w the guidelines in ?an383: si47xx antenna, schematic, layout and design guidelines.? silicon laboratories will evaluate schematics and layo uts for qualified customers. 2. fmod = 1 khz, 30% modulation, a-weighted, 2 khz channel filter. 3. b af = 300 hz to 15 khz, a-weighted. 4. f rf = 1000 khz, ' f = 10 khz. 5. guaranteed by characterization. 6. analog audio output mode. 7. see ?an388: si470x/1x/2x/3x/4x evaluation bo ard test procedure? for evaluation method. 8. v in = 5 mvrms. 9. stray capacitance on antenna and board must be < 10 pf to achieve full tuning range at higher inductance levels.
si473x-b20 14 rev. 0.5 table 9. wb receiver characteristics 1 (v dd = 2.7 to 5.5 v, vio = 1.5 to 3.6v, t a = 25 c) parameter symbol test condition min typ max unit input frequency f r 162.4 ? 162.55 mhz sensitivity 2,3 sinad = 12 db ? 0.9 ? v emf adjacent channel selectivity 25 khz ? 52 ? db audio s/n 2,3,4,5 mono ? 45 ? db audio frequency response low 6 ?3 db ? ? 300 hz audio frequency response high 6 ?3 db 3 ? ? khz notes: 1. to ensure proper operation and receiver performance, follow the guidelines in ?an383: si47xx antenna, schematic, layout and design guidelines.? silicon laboratories will evaluate schematics and lay outs for qualified customers. 2. f mod = 1 khz. 3. ? f = 3 khz. 4. v emf = 1 mv. 5. a-weighted. 6. guaranteed by characterization table 10. reference clock and crystal characteristics (v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit reference clock rclk supported frequencies 1 31.130 32.768 40,000 khz rclk frequency tolerance 2 ?100 ? 100 ppm refclk_prescale 1 ? 4095 refclk 31.130 32.768 34.406 khz crystal oscillator crystal oscillator frequency ? 32.768 ? khz crystal frequency tolerance 2 ?50 ? 50 ppm board capacitance ? ? 3.5 pf notes: 1. the si473x divides the rclk input by refclk_prescale to obtain refclk. there are some rclk frequencies between 31.130 khz and 40 mhz that are not supported. se e ?an332: si47xx programming guide,? table 6 for more details. 2. a frequency tolerance of 50 ppm is required for fm seek/tune using 50 khz channel spacing, sw seek/tune, and wb tune.
si473x-b20 rev. 0.5 15 3. typical am/fm ap plication schematic notes: 1. place c1 close to v dd pin. 2. all grounds connect directly to gnd plane on pcb. 3. pins 1 and 20 are no connects, leave floating. 4. to ensure proper operation and receiver performance, follo w the guidelines in ?an383: si47xx antenna, schematic, layout and design guidelines.? silicon laboratories will evaluate schematics and layout s for qualified customers. 5. pin 2 connects to the fm antenna interface and pin 4 connects to the am antenna interface. 6. rfgnd should be locally isolated from gnd. 7. place si473x as close as possible to antenna jack a nd keep the fmi and ami traces as short as possible. optional: digital audio output 20 19 18 17 16 u1 si473x-gm sen sclk sdio 1 2 3 4 5 15 14 13 12 11 6 7 8 9 10 rst rclk c1 lout rout vbattery 2.7 to 5.5 v gpo1 gpo2/int gpo3/dclk vio 1.5 to 3.6 v fmip c2 c3 x1 rclk gpo3 optional: for crystal oscillator option c5 l1 am antenna optional: am air loop antenna rfgnd ami c5 t1 l2 dout lout/dfs rout/dout gnd vdd nc gpo1 gpo2/int gpo3/dclk dfs nc fmi rfgnd ami rst sen sclk sdio rclk vio dfs r1 r2 r3 dout
si473x-b20 16 rev. 0.5 4. bill of materials component(s) value/description supplier c1 supply bypass capacitor, 22 nf, 20%, z5u/x7r murata c5 coupling capacitor, 0.47 f, 20%, z5u/x7r murata l1 ferrite loop stick, 180 ? 450 h jiaxin u1 si473x am/fm radio tu ner silicon laboratories optional components t1 transformer, 1?5 turns ratio jiaxin, umec l2 air loop antenna, 10?20 h various c2, c3 crystal load capacitors, 22 pf, 5%, cog (optional: for crystal oscillator option) venkel x1 32.768 khz crystal (optional: fo r crystal oscillator option) epson r1 resistor, 2 k ?? (optional: for digital audio) venkel r2 resistor, 2 k ?? (optional: for digital audio) venkel r3 resistor, 600 ?? (optional: for digital audio) venkel
si473x-b20 rev. 0.5 17 5. pin descriptions: si473x-gm gnd pad 1 2 3 17 18 19 20 11 12 13 14 6 7 8 9 4 5 16 10 15 gpo2/int vio dout lout rout gnd rst nc ami rclk sdio vdd fmi rfgnd gpo3/dclk nc gpo1 dfs sclk sen pin number(s) name description 1, 20 nc no connect. leave floating. 2 fmi fm/wb/sw rf inputs. fmi should be connected to the antenna trace. 3 rfgnd rf ground. connect to ground plane on pcb. 4 ami am/sw/lw rf input. ami should be connected to the am antenna. 5r s t device reset (active low) input. 6 sen serial enable input (active low). 7 sclk serial clock input. 8 sdio serial data input/output. 9 rclk external refere nce oscillator input. 10 v io i/o supply voltage. 11 v dd supply voltage. may be connected directly to battery. 12, gnd pad gnd ground. connect to ground plane on pcb. 13 rout right audio line output in analog output mode. 14 lout left audio line output in analog output mode. 15 dout digital output data in digital output mode. 16 dfs digital frame synchronization input in digital output mode. 17 gpo3/dclk general purpose output, crystal osc illator, or digital bit synchronous clock input in digital output mode. 18 gpo2/int general purpose output or interrupt pin. 19 gpo1 general purpose output.
si473x-b20 18 rev. 0.5 6. ordering guide part number* description package type operating temperature si4730-b20-gm am/fm broadcast radio receiver qfn pb-free ?20 to 85 c si4731-b20-gm am/fm broadcast ra dio receiver with rds/rbds qfn pb-free ?20 to 85 c si4734-b20-gm am/fm/sw/lw br oadcast radio receiver qfn pb-free ?20 to 85 c si4735-b20-gm am/fm/sw/lw br oadcast radio receiver with rds/rbds qfn pb-free ?20 to 85 c si4736-b20-gm am/fm/wb broadcast radio receiver qfn pb-free ?20 to 85 c si4737-b20-gm am/fm/wb broadcast radio receiver with rds/rbds qfn pb-free ?20 to 85 c si4738-b20-gm fm/wb broadcast radio receiver qfn pb-free ?20 to 85 c SI4739-B20-GM fm/wb broadcast r adio receiver with rds/rbds qfn pb-free ?20 to 85 c *note: add an ?(r)? at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
si473x-b20 rev. 0.5 19 7. package outl ine: si473x qfn figure 5 illustrates the package details for the si473x. table 11 lists the val ues for the dimensions shown in the illustration. figure 5. 20-pin quad flat no-lead (qfn) table 11. package dimensions symbol millimeters symbol millimeters min nom max min nom max a 0.50 0.55 0.60 f 2.53 bsc a1 0.00 0.02 0.05 l 0.35 0.40 0.45 b 0.200.250.30 l1 0.00 ? 0.10 c 0.27 0.32 0.37 aaa ? ? 0.05 d 3.00 bsc bbb ? ? 0.05 d2 1.65 1.70 1.75 ccc ? ? 0.08 e 0.50 bsc ddd ? ? 0.10 e 3.00 bsc eee ? ? 0.10 e2 1.65 1.70 1.75 notes: 1. all dimensions are shown in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
si473x-b20 20 rev. 0.5 8. pcb land pattern: si473x qfn figure 6 illustrates the pcb land pattern details for the si473x family. ta ble 12 lists the values for the dimensions shown in the illustration. figure 6. pcb land pattern
si473x-b20 rev. 0.5 21 table 12. pcb land pattern dimensions symbol millimeters symbol millimeters min max min max d 2.71 ref ge 2.10 ? d2 1.60 1.80 w ? 0.34 e 0.50 bsc x ? 0.28 e 2.71 ref y 0.61 ref e2 1.60 1.80 ze ? 3.31 f 2.53 bsc zd ? 3.31 gd 2.10 ? notes: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m- 1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximum mate rial condition (mmc ). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. notes: solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes: stencil design 1. a stainless steel, laser-cut, and electro-polis hed stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 1.45 x 1.45 mm square aperture should be used for the center pad. this provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component stand-off. notes: card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si473x-b20 22 rev. 0.5 9. additional reference resources contact your local sales representative s for more information or to obtain copies of the following references: ? en55020 compliance test certificate ? an332: si47xx programming guide ? an383: si47xx antenna, schematic, layout, and design layout guidelines ? an388: si470x/1x/2x/3x/4x eval uation board test procedure
si473x-b20 rev. 0.5 23 n otes :
si473x-b20 24 rev. 0.5 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: fminfo@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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